1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a hybrid memory device using a static RAM cell and a plurality of ROM cells.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional hybrid memory device for driving a memory cell array 1 having a static RAM cell 11 and a ROM cell 12. As shown in FIG. 1, a conventional hybrid memory device for driving the memory cell array 1 includes a static RAM control unit 2 for selecting the static RAM cell 11 in accordance with a write control signal /WE and a read control signal /RE; a static RAM decoder 3 for decoding an address ADD temporarily stored in a static RAM buffer 4 using a static RAM enable signal /CSSRAM; a static RAM data input/output unit 5 for storing data in the static RAM cell 11 in accordance with the static RAM enable signal /CSSRAM or for outputting the data stored in the static RAM cell 11; a ROM control unit 6 selecting the ROM cell 12 in accordance with the read control signal /RE; a ROM decoder 7 for decoding an address ADD temporarily stored in a ROM buffer 8 in accordance with a ROM enable signal /CSROM; and a ROM data output unit 9 for outputting data stored in the ROM cell 12. The operation of the conventional hybrid memory device will now be described with reference to FIGS. 2A-2G.
As shown in FIGS. 2A-2G, in the first interval (I) when the ROM enable signal /CSROM (FIG. 2C) is a high level and the static RAM enable signal /CSSRAM (FIG. 2B) is a low level, the address ADD temporarily stored in the static RAM buffer 4 is decoded by the static RAM decoder 3. Using the decoded signal, the desired static RAM cell 11 of the memory cell array 1 is selected and enabled. Here, when the write control signal /WE (FIG. 2D) is a high level and the write control signal /RE (FIG. 2E) is a low level, the data stored in the selected static RAM cell 11 are externally outputted by the static RAM data input/output unit 5. In contrast, when the write control signal /WE (FIG. 2D) and the read control signal /RE (FIG. 2E) are respectively low and high levels, the external data DIN, /DIN are stored in the static RAM cell 11 selected by the static RAM data input/output unit 5.
In the second interval (II), both the static RAM enable signal /CSSRAM (FIG. 2B) and the ROM enable signal /CSROM (FIG. 2C) are high levels, and the hybrid device is in a stand-by mode. That is, an external dis-able state is set.
In the third interval (III), when the static RAM enable signal /CSSRAM (FIG. 2B) is a high level and the ROM enable signal /CSROM (FIG. 2C) is a low level, the address ADD stored in the ROM buffer 8 is decoded by the ROM decoder 7. Thus, the desired ROM cell 12 of the hybrid memory cell array 1 is selected with respect to the decoded signal and enabled. Here, when the read control signal /RE is a low level, the data temporarily stored in the enabled ROM cell 12 are externally outputted by the ROM data output unit 9.
However, the conventional hybrid memory device using the static RAM cell 11 and the ROM cell 12 has a problem in that the static RAM cell 11 and the ROM cell 12 respectively employ peripheral circuits such as the buffers 4, 8 and the decoders 3, 7. As a result, the conventional hybrid memory device occupies an unnecessarily large layout area.